DAQ Hardware

The DAQ hardware configuration is shown on Fig. 1. It's built around the VME system crate. That crate contains two PCI-VME bridges interfacing two PC's with VME, the interrupt module, the readout controller for dedicated front-end electronics, the memory module for readout controller data buffering, the VME-CAMAC interface, and interface for front-end electronics control link.

The PCI-VME bridge (SBS-BiT3 mod.617 [2]) provides the mapping of the PCI bus address space to the VME bus address space giving the transparent access from PC to VME bus locations as locations in its own memory with 2.2 $\mu$sec access time. It has a built-in DMA controller that can copy block of data from VME modules to PC memory with speed up to 0.4 $\mu$sec per word. Additionally the bridge can transfer selected VME backplane interrupts into PCI bus interrupts that can be served by CPU.

The interrupt module (CES RCB CORBO 8047 [3]) transfers external interrupts into VME backplane interrupts IRQ1 - IRQ7. It has 4 independent channels each of those has the trigger pulse input generating the VME interrupts and the BUSY level output that is set by trigger pulse and reseted by software. Each channel might be assigned to the own interrupt level. The DAQ uses three interrupt channels for START OF BURST, END OF BURST and EVENT interrupts generation.

The readout controller is started by event trigger pulse, autonomously reads the data from dedicated front-end electronics and writes those through VME bus into the buffer memory module with speed up to 0.6 $\mu$sec per 4 bytes word. It is activated by DAQ computer at START OF BURST time and deactivated at END OF BURST time. There is a test readout mode when controller isn't activated and data readout is started by EVENT interrupt and done by software directly using the VME front-end control.

We use the software driver developed by N.Kruszynska at NIKHEF [4] with slight modifications. We decided that in our case the driver has to: (i) establish the required PCI-VME mapping and (ii) reschedule the interrupt servicing process when interrupt occurs. All VME transactions have to be done not by the driver but by that process using the memory mapping. Technically the interrupt servicing process setups the mapping by the "mmap" system directive and goes to read the status of VME bridge by the "read" system directive. When an interrupt arrives the process is rescheduled and runs having a single interrupt status word. Finishing the interrupt processing the process resets the proper BUSY level at the interrupt module and again goes to read status. The implemented interrupt processing scheme provides a reasonable event readout time: in the interrupt mode it is $\sim 30 \mu sec + 2.2 \mu sec * NUMBER\_OF\_DATAWORDS$ at Pentium150 PC measured as length of BUSY level by oscilloscope.

The DAQ uses the set of 6 PC's running the Linux operating system and linked into LAN by 100 MBits Ethernet. Two of those are equipped by PCI-VME bridges and work as primary DAQ computers. The first serves the external interrupts and acquires the data from front-end electronics. The second one is the slow control computer that executes such tasks as trigger logic control, beam-line magnets control etc. The remaining computers work as the secondary DAQ computers that host the control, monitoring and data analysis software.

Figure 1: ISTRA+ DAQ hardware.